/***************************************************************************/ 
/*	Copyright � 2004 Altera Corporation. All rights reserved.             */ 
/* Altera products are protected under numerous U.S. and foreign patents,  */ 
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/***************************************************************************/ 
 
/***************************************************************************/ 
/* File: pwm_task_logic.v                                                  */ 
/* Description: This module contains the core of the pwm functionality.    */ 
/*    The clock_divide and duty_cycle inputs are used in conjunction with  */ 
/*    a counter to determine how long the pwm output stays high and low.   */ 
/*    The output is 1 bit.                                                 */ 
/***************************************************************************/ 
 
module pwm_task_logic 
( 
	clk, 
	pwm_enable, 
	resetn,  
//	clock_divide, 
	duty_cycle, 
	pwm_out 
); 
 
//Inputs 
input clk;				//Input Clock to be divided 
//input [31:0] clock_divide;	//Clock Divide value 
input [31:0] duty_cycle;	//Duty Cycle vale 
input pwm_enable;			//Enable signal 
input resetn;			//Reset 
 
//Outputs 
output pwm_out;			//PWM output 
 
//Signal Declarations	 
reg [31:0] counter;		//PWM Internal Counter 
reg pwm_out;			//PWM output 
	 
//Start Main Code	 
// this code only happens at a clock edge 
// if inverse of resetn is true 
//
//
//
//
//
//
//// -- purpose: divide system clock down from 50Mhz to 1khz
//// -- type   : sequential
//// -- inputs : clk, resetn
////  -- outputs: slow_clk
//  clockdiv: process (clk, resetn)
//  begin  -- process clockdiv
//    if resetn = '0' then                -- asynchronous reset (active low)
//      slow_clk <= '0';
//      clock_div <= X"0000";
//    elsif clk'event and clk = '1' then  -- rising clock edge
//      if clock_div = conv_unsigned(X"0064",16) then
//        clock_div <= conv_unsigned(X"0000",16);
//        slow_clk <= not slow_clk;
//      else
//        clock_div <= clock_div +1;
//      end if;
//    end if;
//  end process clockdiv;


always @(posedge clk or negedge resetn)         //PWM Counter Process 
begin 
	if (~resetn)begin 
		counter = 0; 
	end 
	else if(pwm_enable)begin 
		if (counter >= X"0064")begin 
			counter = 0; 
		end 
		else begin	 
			counter = counter + 1; 
		end 
	end 
	else begin 
		counter = counter;			 
	end 
end 
 
 // This part controls the output bit
 // if inverse of resetn is true then set PWM as 0
 
 // if pwm_enable is true then carry on else set pwm_out low
 // 	IF counter is greater than or equal to the duty cycle set pwm_to high END 
 // 	IF counter is 0 set pwm_out to 0 else (counter is not 0) keep pwm_0 the same
 //
 
always @(posedge clk or negedge resetn)      //PWM Comparitor 
begin 
	if (~resetn)begin 
		pwm_out = 0; 
	end 
	
	else if(pwm_enable)begin 
		if (counter >= duty_cycle)begin 
			pwm_out = 1'b1; 
		end 
		
		else begin 
			if (counter == 0) 
				pwm_out = 0; 
			else 
				pwm_out = pwm_out; 
			end 
		end 
	else begin 
		pwm_out = 1'b0; 
	end 
end 
 
	 
endmodule 



